meeting date: 24 jan 2006
attending: Arpad Muranyi, Bob Ross, Mike LaBonte, Ian Dodd, Walter Katz

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Review of ARs:

AR: Todd contact Xilinx about DesignCon IBIS summit again
- done

AR: Todd prepare overview presentation for IBIS summit
- TBD 

AR: Arpad prepare technical presentation for IBIS summit
- TBD

AR: Mike cleanup website
- Almost done

AR: Mike finish documentation examples.
- TBD

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Conversion script discussion
- Mike ran Paul's script and gave feedback to Paul
  - Make the script extract custom buffer definitions for each
    buffer found in the IBIS file.
  - Add option to set output file name.
- Are we creating custom buffer definitions for each instantiation?
  - Array parameter passing would make this unnecessary
    Not there yet though:
    - New HSPICE can take array parameters, but must match declared size.
    - Could use pre-defined size and pad the passed array data.
    - How to make code ignore the extra points?
- Should the script create define statements or buffer module definitions?
  - Paul did what was asked of him, although Arpad hasn't run it yet.
  - Mike's feedback may have misled Paul.
- How to handle multiple buffer models?
  - Model maker will run Paul's script and ether insert the output into
    VerilogA template inline, or `include it from an external file.
  - There may be a scoping problem because the defines produced always have
    the same names
    - No problem, LRM section 11.3.1 specifies that defines can change, and
      code always uses the value of the previous define at compile time.
    - There is an undefine provision anyway, in case it is needed.
- Paul wrote a very complete script.
- Arpad close to releasing new versions of library.

AR: Mike contact Paul to give corrected feedback

Website cleanup
- Mike found over 1000 files in his 'macromodel' directory that
  are not on the IBIS website.
- At least the minutes should be brought up to date for now.

AR: Mike bring website up to date with respect to minutes

Compatibility among simulators
- Assuming we want to run source for External Model directly in AMS languages.
- But it probably will not work the same in different implementations
  - We avoided expressions for this reason.
  - Simulators do not seem to be fully implementing the LRM.
- Simulator companies could have a pre-processor to fix the input AMS language
  for the specific target Verilog or VHDL simulator
  - This could solve the array length problem, for example.
  - This is a work-around.
  - EDA companies eventually need to implement full LRM.
  - That will take time.
  - SPICE simulators need a pre-processor anyway.
- Discussion of language subset last week was related to this issue.

Behavioral AMS vs. Macromodels
- Behavioral AMS is still better than macromodel, for future flexibility.
  - Difficult to do receiver models with macromodels.
    - Not enough building blocks in our library for this.
  - Macromodel idea was chosen to support SPICE substitution
- Macromodels help define a subset of the LRM that is required
  - But defining a subset of the LRM may make EDA companies "lazy".
  - EDA companies have contracts with customers to implement specific subsets.
- Concern about support requirements trying to implement full LRM.
- How to define the AMS subset needed?
  - Consider each language feature one at a time?
  - Do we need a task force for receiver modeling?
    - D.C. Sessions was pushing for this long ago
      - JEDEC solutions were simplistic.
    - Macromodels can model receivers, but become very complex.

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Next meeting: Tuesday 31 jan 2006